Wafer Back Grinding

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Wafer back grinding, or wafer thinning, is a process that reduces the thickness of semiconductor materials in order to enable high-density packaging and stacking of integrated circuits (ICs). Silicon and other semiconductors are usually 750 mm or thinner, and this is done to prevent warping during the subsequent high-temperature processing steps. Back-grinding can also be called “thinning,” as it removes some of the material from the wafer.

Process of thinning semiconductor wafers

The process of thinning semiconductor wafers involves grinding them to achieve a final thickness of 50 to 70 um. It is an important process in the semiconductor manufacturing process and involves three main steps. The coarse grind removes the majority of material while the fine grind removes it at a slower rate. The rate at which the material is removed is controlled by the grind recipe. It is generally faster to coarse grind than to fine grind, but a finer grain size will result in greater material removal.

ADP-DCE is a recent method for thinned silicon wafers. Ar/CF 4 plasma is used in this method. It is performed at a rate of 20 um/min and results in a uniformity ms of 0.3 nm. The surface is also rougher than expected, with several nanometer-high needle-like hills visible. This may be an effect of anisotropic etching.

After the backside thinning step, the wafers are mounted to a concentric glass disk.
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This support system keeps the wafers in place, while removing residual microcracks. The backside spin-etching step rounds these grooves and removes residual microcracks. The backside spin-etching step rounds the front side grooves and helps singulate the chip.

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Techniques used in back-grinding

Wafer back-grinding is an integral process that entails placing a wafer on a chuck table and advancing a grinding wheel against it. Some systems grind one wafer at a time while others grind several simultaneously. The back grinding process can be controlled by measuring the related parameters. The wheel’s spinle current is measured to determine the grinding wheel’s friction with the wafer. The grinding wheel’s capacitance is also monitored during the process.

A back grinding device for semiconductor wafers includes a first vacuum chuck stage 23 that has a diameter slightly larger than the front surface of the wafer. This protects the front of the wafer from vibrations caused by the grinding wheel. Also, because the protection tape 22 is smaller than the front surface of the wafer, it can be used as a guide for the grinding wheel. Techniques used in wafer back-grinding processes are not limited to those mentioned here, and the process can be modified for a variety of applications.

Wafer back-grinding involves the removal of a thin layer of material from the silicon wafer. This is done by using a series of grinding wheels. The first wheel has a coarse grit. The subsequent wheels are finer, allowing the silicon wafer to become ultra-thin. Wafer back-grinding machines can remove 100-um thick logic gates, 50-um thick DRAM memory, and thirty-um-thick MEMS memory. A high-resolution measurement is necessary before a wafer is shipped to a customer. This is where MTI Instruments comes in.

Impact of back-grinding on mechanical properties of semiconductor wafers

As the demand for hand-held and smaller semiconductor devices increases, the need for thin wafers is also increasing. Increasingly, 300-mm thick and bumped wafers are used for such applications. This makes thinning and back grinding equipment an increasingly critical issue in semiconductor assembly. Back grinding leaves a characteristic scratch pattern on the wafer. In particular, certain locations on the wafer show primarily vertical scratches.

The depth of scratches and the roughness of the back side are directly related to the strength of the semiconductor die. It is therefore important to get the back side surface of the wafer as smooth as possible. Micro-scratches are also caused by large particles that may be present in the incoming slurry or the polishing pad. While process optimization can help minimize or eliminate micro-scratches, the process cannot completely eliminate them.

Microdefects are also common and can be caused by the process of back grinding. The subsurface layer of a silicon wafer is damaged by grinding, and the damage can be simulated by atomistic simulation. The subsurface layer is on the nanometer scale and difficult to separate from the undamaged silicon. This is a common problem in semiconductor manufacturing, and the atomistic simulation can help us to better understand and predict how such a process might impact the mechanical properties of silicon wafers.

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